1. Field of Invention
This invention relates to a DRAM (Dynamic Random Access Memory) cell of highly integrated semiconductor storage device, and a method for manufacturing the same, and more particularly to a DRAM cell having a SDTAS (Side-Wall Doped Trench and Stacked Capacitor) structure which can increase the capacitance of capacitor and reduce the area of cell by reducing the width of MOSFET, and a method for manufacturing such cell.
2. Related Application
A method for forming a selectively doped diffusion region using a photoresist etch back technology is fully described in U.S. Ser. No. 07/381,288, entitled: A Method For Manufacturing A Trench Capacitor Using A Photoresist Etch Back Process and a self-aligned contact process is fully described in U.S. Ser. No. 07/381,289, entitled: Dynamic Random Access Memory Cell and Method, both applications filed on Jul. 18, 1989, said applications being expressly incorporated herein by reference as if fully set forth hereat.